19 September 2018
Hotel Radisson Blu, Bengaluru

Call for Paper

Abstract & Paper Submission Schedule

Call for Abstract Submission opens 10 April 2018
Call for Abstract Submission closes 09 September 2018
Acceptance notification 11 September 2018
Final Paper Submission due on 15 September 2018
Conference and Presentation Day 19 September 2018

Guidelines for Submission

  • Guidelines for Abstract
  • Guidelines for Paper
  • Guidelines for Presentation

▪ Proposed Paper title

▪ An introduction specifying the context and motivation of the submission.

▪ Description of the specific contributions of your work.

▪ Summary highlighting results.

▪ Mandatory to use the suggested template format .

▪ Must be approximately 2 pages and may include figures/diagrams/charts/tables

▪ References if required

▪ Paper length should be around 4+ pages, though there is no limitation on the length of the paper submitted

▪ The objective of the study and title/ An introduction that specifies the context and motivation of the submission.

▪ How the problem statement mentioned will provide solution or how the pain point will be eradicated by the solution you have proposed in your study.

▪ Mention the methodologies proposed/executed in conjunction with the study.

▪ A summary that highlights results.

▪ The parameters of successful implementation of the study proposed/done.

▪ Must use the suggested template format

▪ References/Bibliography, if deemed necessary.

▪ Total presentation time is 25 minutes. The presentation should last for 20 minutes maximum with 5 minutes reserved for Q & A.

▪ The objective of the study and title/ An introduction that specifies the context and motivation of the submission.

▪ How the problem statement mentioned will provide solution or how the pain point will be eradicated by the solution you have proposed in your study.

▪ Mention the methodologies proposed/executed in conjunction with the study.

▪ A summary that highlights results.

▪ The parameters of successful implementation of the study proposed/done.

▪ Must use the suggested template format (Attached with this email).

▪ Must be a minimum of 7-8 slides with maximum upto 15 slides (including figures/diagrams/charts/tables)

▪ References/Bibliography, if deemed necessary.

Criteria for Selection of Paper

The paper will be evaluated by the panel of judges appointed by Truechip. The Top 4 OR 5 Papers will be selected out of the total submissions for each track( DV Track and Phy Des & DFT Track) who will present at the conference.

▪ Significance of study

▪ Technical Knowledge

▪ Exclusivity of content

▪ Methodologies used

▪ Innovation used

Suggested Topics for Papers

DV Track

Verification & Validation


▪ Advanced methodologies and   testbenches

▪ Verification processes, regressions and   resource management

▪ Debug and analysis of complex designs

▪ Multi-language design and verification

Machine Learning & Big Data


▪ Automating the Optimization of   Verification Processes

▪ Coverage metrics and data analysis

▪ Performance modeling and/or analysis

Design & Verification reuse and Automation I


▪ Bridging verification and validation   across multiple engines

▪ SoC and IP integration methods and   tools

▪ Automated stimulus generation   methods

▪ Configuration management of IP and   abstraction levels

Design & Verification reuse and Automation II


▪ High-level synthesis from ESL languages

▪ Bridging virtual prototyping, simulation,   emulation and/or FPGA prototyping

▪ Interoperability of models and/or tools

Low-Power Design & Verification


▪ Low-power design and verification

▪ Clock domain crossing verification

▪ Power modeling, estimation and   management

Safety-Critical Design & Verification


▪ Verification and DO-254 compliance

▪ Automotive ISO 26262 Design and   Verification Challenges

▪ Medical or Industrial Verification   Challenges

▪ Requirements-Driven Verification   Methodologies

▪ IP protection and security

Additional Topics 1


▪ Usage of specialized design and   verification languages such as   SystemVerilog, SystemC, and e

▪ Assertions in SVA or PSL

▪ The use of general purpose and scripting   languages such as C, C++, Perl, Python, Tcl   and others

▪ The use of AMS languages

▪ IoT Applications

Additional Topics 2


▪ Usage of Electronic Design Automation   (EDA) tools such as simulation,emulation,   formal verification, virtual prototyping   and/or FPGA prototyping FPGA-based   designs

▪ Applications of the new Accellera   Portable Stimulus Standard

▪ Applications of design patterns or other   innovative language techniques

Physical Design & DFT

Yield Analysis and Modeling


▪ Defect/fault analysis and models.

▪ statistical yield modeling; diagnosis.

▪ critical area and other metrics.

▪ Multi-language design and verification.

Testing Techniques


▪ Built-in self-test.

▪ delay fault modeling and diagnosis.

▪ testing for analog and mixed circuits.

▪ online testing; signal and clock integrity

Design For Testability in IC Design


▪ FPGA, SoC, NoC, ASIC, low power design   and microprocessors

Error Detection, Correction, and Recovery


▪ Self-testing and self-checking design

▪ error-control coding

▪ fault masking and avoidance

▪ recovery schemes, space/time redundancy

▪ hw/sw techniques

▪ architectural-specific techniques

▪ system-level design-time or runtime   strategies

Dependability Analysis and Validation


▪ Fault injection techniques and frameworks

▪ system's dependability and vulnerability   characterization

Repair, Restructuring and Reconfiguration


▪ Repairable logic.

▪ reconfigurable circuit design.

▪ DFT for on-line operation; self-healing.

▪ reliable FPGA-based systems.

Design for Defect and Fault Tolerance


▪ Reliable circuit/system synthesis.

▪ radiation hardened/tolerant processes and   design.

▪ design space exploration for dependable   systems.

▪ transient/soft faults and errors.

Aging and Lifetime Reliability


▪ Aging characterization and modeling;   design and run-time reliability, thermal,   and variability management and recovery.

Dependable Applications and Case Studies


▪ Methodologies and case study applications   to Internet of Things,automotive, railway,   avionics and space, autonomous systems,   industrial control, etc.

Emerging Technologies


▪ Techniques for 3D stacked ICs, quantum   computing architectures, microfluid   biochips, etc.

Design for Security


▪ Fault attacks.

▪ fault tolerance-based countermeasures.

▪ hw security assurance.

▪ hw trojans.

▪ resistance to persistent DoS, security vs.   reliability trade-offs, interaction between   VLSI test, trust, and reliability.