Uday Mishra is currently Director of Engineering with Western Digital at Bangalore. He is heading the SoC Design group of 100+ engineers responsible for high performance ASIC development for multiple product lines within Western Digital. He is regarded as one of the foundation stone for success story of Western Digital India in delivering high quality ASICs since last twelve years. Uday has deep knowledge of all the phases of ASIC development gained through multiple ASIC tape outs during his twenty one years of VLSI industry experience. His area of expertise is in developing high performance architectures and low power methodologies to cater for Enterprise, Embedded & Mobile Flash Storage Product ASICs. Uday gained his Post Graduation degree from Royal Melbourne Institute of Technology, Melbourne, Australia thereafter worked with Freescale Australia for six years. He earned his Bachelor's degree from University of Delhi and started his career with defence sector working in embedded field for initial three years.

Prasad Joshi has over 19 years of experience in Semiconductor industry & has played various leadership and management roles. He works with IBM India as a Senior Manager and presently leads the development of various interface IPs for IBM's P and Z Server class processors such as high speed SERDES. He has keen interest in front-end design tools & methodologies in general and specifically in functional verification. He has actively participated in various industry events as an organiser as well as a speaker.

Director Automotive Digital IP for India operations. He has been engaged with Automotive SoC / IP development in NXP for past 10 years, in various roles including SoC Chip lead, Global Digital IP Manager and now as a Director R&D, Digital IP. He has been involved in development of multi-million gate SoCs meant for Driver Information Systems. He and his team have been working on IP and Subsystem development across 12 domains including Automotive Safety, Security, Customer Processors for Radar, Vision ADAS, Graphics, Body Electronics and more. Before NXP, he has also worked in various capacities with Agilent Technologies India, NEC Australia in Melbourne and Altima Corporation in Japan. He has overall 18 years of experience. He did his Engineering from IIT-Roorkee and has also done MBA from IIM-Lucknow.

Verification Manager Infineon Technologies. Overall 18+ years of experience in digital design, functional verification of several generations of ASICs/SoC chips and EDA tools/methodology development/support. Managed teams across Mobile/Chipset/GPU/CPU/Automotive domains at various levels (unit,sub-block,full-chip and system). Handled varied responsibilities in logic design/pre and post-Si verification/EDA/DFT in Intel/IBM/Infineon.

He had completed his masters in Microelectronics from IIT,Madras.

Principal Engineer, ASIC Verification Western Digital. With more than 14 years in ASIC Verification, spanning a variety of tools, flows, processes and methodologies. Began career in Texas Instruments India in 2003 and after 10 years, joined SanDisk India (now Western Digital) in 2013. As Principal Engineer, has presented technical papers, led teams towards execution, and over the span of the career, delivered services for mission-critical systems of industry leaders

Verification Lead Texas Instruments. Did his Masters in VLSI from Indian Institute of Technology, Delhi in 2000. He is part of TI India MCU group and working as verification lead. He has worked on various successful devices and managed the design verification (DV) domain from single core low cost/low power to triple core complex high performance devices

Program Manager MediaTek. 18 years of solid experience in ASIC design, verification, synthesis and timing closure. Having strong knowledge of VHDL/Verilog, logic synthesis, dft, timing/power analysis, logic equivalence, verification strategies (RTL as well as gate level), FPGA, zebu and silicon validation. Successfully led front end design teams like DTV, DRP and OMAP1710. Experience with scheduling and project planning on multi-site projects.