TrueConnect 2020 Conference Date Coming Soon

Conference Detail

TrueConnect 2019
Date: Thursday, November 14, 2019
Time: 9:00 AM to 5:30 PM (IST)
Venue: Hotel Radisson Blu (Formely known as Park Plaza), 90-4 Outer Ring Road,Marathahalli, Bengaluru

Many organizations have a commitment to their communities, be it through philanthropic efforts or hands-on projects. For Truechip, however, this commitment is more than just part of what we do. Having this in center, TrueConnect 2019 - "Enriching collaboration for innovative excellence" is the first edition of the Verification & Design conference from the house of Truechip. This one-day conference will focus on sharing and presenting innovative studies done by industry professionals in the field of verification IP, Physical Design, DFT product, solutions and services. The conference will also be having Key notes and panel discussions along with the Key notes by Industry leader.

Main Attraction

Paper & Presentations

Industry professionals from Verification & Design industry domain will present slides and the best presentation(s) will be chosen and will be bestowed awards.

Keynote Speakers & Panel Discussion

Listen to the Industry Experts- Immerse yourself in the treasures of the wise word - Step into the world of Design and automation- Explore migration patterns through the medium of discussions - Get to grips with the UVM language - Uncover the meaning of SoC - Discover a 'New FAB'

Industry experts will share thoughts on the current global trends in the field of design & verification space, opportunities, challenges, strength and weakness of the sector and the vast scalability of this domain

The Exhibition Gallery

Check out the new products and solutions from Industry conglomerate where they would be showcasing the innovative technology to the industry professionals

Networking Opportunities

We recognize the value of providing the right environment to learn about new business opportunities or contacts. Trueconnect is an ideal event to expand one's knowledge and meet new contacts in the industry along with sharing novel practices.

Keynote Speaker & Panel Profile 2019

Thursday November 14, | EVENT TYPE: KEYNOTE | Guest Speaker

Speaker: Anurag Gupta, Sr. Director-ASIC, Western Digital

Anurag Gupta

Anurag Gupta, Senior Director of Engineering, leads Western Digital's India large ASIC organization of 350 members and responsible for end-to-end development of memory controller ASICs, IP & RISCV core.
Prior to Western Digital, he set up and headed LG' mobile SOC development group in India and developed two generation of Mobile Application Processors. His earlier major work experience includes R&D engineering technical & management roles at Freescale Semiconductor (Automotive Division), Texas Instruments (Wireless division). He had headed Asia Pacific patent review committee in Freescale Automotive division and was elected as MGTS (in TI) and MMTS (in Freescale) titles for his innovative technical contribution and impact to business. He has lead various DSP subsystems and mobile application processors, OMAP & Modem chips in his TI tenure and multiple Automotive SoCs (ADAS, Safety, Cluster, PowerTrain) & Microcontrollers for Industrial automation in his Freescale tenure.

Thursday November 14, | EVENT TYPE: KEYNOTE | Invited Keynote

Speaker: Ajay Nawandhar,Sr. Director Engineering - Qualcomm India Pvt Ltd

Biography: Ajay Nawandhar is Sr. Director Engineering and heads the Multimedia and GPU (MMG) group at Qualcomm India Pvt. Ltd. Ajay is responsible for leading development of Multimedia & Graphics which involves GPU, Camera, Video, Display Audio and Machine learning IPs in India. He leads the R&D Organization spread across two locations (Noida, Bangalore) and consisting of nearly 300 employees delivering these IPs across tiers (performance levels). He has played a pivotal role in the steep growth of the BDC MMG team over the past 6 years, demonstrating relentless passion for execution, innovation, and great partnership with global stake holders. Ajay has over 19 years of experience in Semiconductor industry & has played various technical, leadership and management roles. He holds Two US patents in the areas of low power MMG design. Ajay believes work and fun need to go hand in hand and hence has been involved in lot of Organizational activities apart from his regular responsibilities. Before joining Qualcomm, Ajay worked with Intel and ControlNet. Ajay holds a bachelor's degree in electronics engineering from Shivaji University, Maharashtra, India.

Thursday November 14, | EVENT TYPE: KEYNOTE | Invited Keynote

Speaker: Hitesh Garg, Sr. Director & Site Head, NXP Semiconductors

Hitesh Garg

Hitesh Garg is Director and Site Head of NXP Bangalore. In his engineering role, he is responsible for building world class Analog IPs for NXP Products, with special focus on Data Convertors, Sensors and Power Management. His teams are busy in designing differentiating IPs/Products in areas of Security and Connectivity, ADAS, In-Vehicle Networking and Smart Car Access.
Hitesh has more than 24 years of experience in Analog Mixed Signal product development. Prior to NXP, Hitesh has worked in Conexant Systems, Microchip Technologies and State owned Semiconductor Complex Limited in various technical and lead roles.
Hitesh holds a Bachelors degree in Electronics & Communication and a Post Graduate Degree in Management from IIM Bangalore.

Hon'ble Jury Member & Panelist Mr. Vijay Chinchole,Director,Western Digital

Mr. Vijay Chinchole

Heading IP verification team in STM. Total 18+ Years of Pre-Silicon Verification in various Role and Capacity in SoC, IP, Subsystem level Functional Verification.
In past, worked with Texas Instruments, Infineon, AMD and Intel. Also very acquitted with latest UVM, Formal Methodologies and Automation. Granted 20+ Trade Secrets and 10+ Patents filing under process, till now. Completed BTech from COEP [College of Engineering Pune] and MTech from IISc [Indian Institute of Science].
Hobbies are playing Badminton, Photography, Blogging, and Poems.

Verification Panelist: Mr. Omprakash Jha

Principal Engineer, ASIC Verification Western Digital. With more than 16 years in ASIC Verification, spanning a variety of tools, flows, processes and methodologies. Began career in Texas Instruments India in 2003 and after 10 years, joined SanDisk India (now Western Digital) in 2013. As Principal Engineer, has presented technical papers, led teams towards execution, and over the span of the career, delivered services for mission-critical systems of industry leaders

Verification Panelist: Mr. Udaya Napa, Sr. Manager - Verification Qualcomm

Mr. Udaya napa

2 decades + of Industry experience,Had Opportunity to work on company's first HDL-based ASIC in 1998 (American Megatrends, now Broadcom).Worked across domains: Storage/Networking/Telecom/Mobile.Have handled 20+ Tapeouts with 8 in Lead role.Worked across verification, acceleration and emulation.

Verification Panelist: Mr. Sriram V, GPU Performance Validation Lead, Intel.

Mr. Sriram V

Has 19+ years of experience in ASIC design, verification in various domains and roles.
Started career with ST Microelectronics and worked on design and verification of image processing IPs. In Intel worked on verification of Memory controller hub and moved on to GPU validation.
Currently technical lead for GPU performance validation focusing on integrated, discrete and compute GPUs.

Verification Panelist: Sudhakar Reddy, Manager, Infineon Technologies

Verification Manager Infineon Technologies. Overall 18+ years of experience in digital design, functional verification of several generations of ASICs/SoC chips and EDA tools/methodology development/support. Managed teams across Mobile/Chipset/GPU/CPU/Automotive domains at various levels (unit,sub-block,full-chip and system). Handled varied responsibilities in logic design/pre and post-Si verification/EDA/DFT in Intel/IBM/Infineon.