19 September 2018
Hotel Radisson Blu, Bengaluru

Conference Detail

TrueConnect 2018
Date: Wednesday, September 19, 2018
Time: 9:00 AM to 5:30 PM (IST)
Venue: Hotel Radisson Blu (Formely known as Park Plaza), 90-4 Outer Ring Road,Marathahalli, Bengaluru

Many organizations have a commitment to their communities, be it through philanthropic efforts or hands-on projects. For Truechip, however, this commitment is more than just part of what we do. Having this in center, TrueConnect 2018 - "Enriching collaboration for innovative excellence" is the first edition of the Verification & Design conference from the house of Truechip. This one-day conference will focus on sharing and presenting innovative studies done by industry professionals in the field of verification IP, Physical Design, DFT product, solutions and services. The conference will also be having Key notes and panel discussions along with the Key notes by Industry leader.

Main Attraction

Paper & Presentations

Industry professionals from Verification & Design industry,Physical Design and DFT domain will present slides and the best presentation(s) will be chosen and will be bestowed awards.


Keynote Speakers & Panel Discussion

Listen to the Industry Experts- Immerse yourself in the treasures of the wise word - Step into the world of Design and automation- Explore migration patterns through the medium of discussions - Get to grips with the UVM language - Uncover the meaning of SoC - Discover a 'New FAB'

Industry experts will share thoughts on the current global trends in the field of design & verification space, opportunities, challenges, strength and weakness of the sector and the vast scalability of this domain


The Exhibition Gallery

Check out the new products and solutions from Industry conglomerate where they would be showcasing the innovative technology to the industry professionals


Networking Opportunities

We recognize the value of providing the right environment to learn about new business opportunities or contacts. Trueconnect is an ideal event to expand one's knowledge and meet new contacts in the industry along with sharing novel practices.


Laughter & Comedy Show

All work and no play makes jack a dull boy. Enjoy the rejuvenating high energy comedy show-An act unlike anything you've ever experienced before-A sumptuous entertainment feast !.


Keynote Speaker & Panel Profile 2018


Wednesday September 19, | EVENT TYPE: KEYNOTE | Invited Keynote

Speaker: Abhijit Dutta,Director - High voltage AMS, BU Automotive,Site head - NXP Bangalore

Biography: Abhijit Dutta received an Engineering degree from the Institute of Radio Physics & Electronics, University of Calcutta, in the year 1985, after receiving his graduate degree in Physics from University of Calcutta.

He joined the Tata Institute of Fundamental Research (TIFR) and worked in the Radio Astronomy group for more than 10 years. He built the digital phase shifter for the Ooty Radio Telescope and later led the team to build a complex online spectral correlator system for the Giant Meterwave Radio Telescope (GMRT) near Pune, which is the world's largest radio telescope working at meter wavelength.

During his long experience in Semiconductor Industry with focus on chip design in companies like Cadence, Intel, Cisco and presently in NXP Semiconductors, Abhijit has built several R&D teams producing ASICs for microprocessors, networking switches and chips for digital TVs. In the last 12 years in NXP semiconductors, and in the last several years in designing chips for automotive electronics. In his current position as Director of the high voltage analog mixed signal design he reports to the CTO of NXP's automotive business and also heads the Bangalore design center which has about 900 engineers.


Wednesday September 19, | EVENT TYPE: KEYNOTE | Invited Keynote

Speaker: Peter Lefkin, Managing Director, MIPI Alliance

Peter Lefkin has been providing leadership and guidance to the standards development community for more than 20 years. Since 2011, he has served as the managing director of MIPI Alliance, responsible for all MIPI activities and operations, from strategy development to implementation. As MIPI's senior staff executive, he also serves as secretary on the MIPI Alliance Board of Directors.

Peter's background includes previous leadership roles at the American National Standards Institute, Motorola and the IEEE Standards Association. As COO/CFO for IEEE Industry Standards and Technology Organization (IEEE-ISTO), he was instrumental in the formation of multiple standards groups, including the founding of MIPI Alliance in 2003.


Verification Panelist: Baskar Rudhramurthy,Manager, Global Foundries

Has 17 years of experience in ASIC Design, Verification and Functional Safety (Automotive). Worked with various semiconductor customer likes Renesas, Broadcom, Panasonic, Intel, Canon, etc. Experience in semiconductor domains like Automotive, Consumer Electronics and Networking.Played roles like customer Interface, consultant and account owner (grown business within India and outside).


Physical Design Panelist: Pradeep Kothari,Technologist, Western Digital

have 11+ years of experience working in VLSI industry where he worked with AMD, Indea systems, Intel.Has worked on many project across technologies and foundries . AMDs fist FUSION APU SOC , first series of WPU , Google's Pixel core processor to name few. Currently he is leading implementation as well as methodology activities for varies PD flows and technology at WD Pradeep has done BE in Electronics and Telecommunication from NMU Jalgaon in year 2003. He did his MS in VLSI design from JNTU Hyderabad in year 2007


Verification Panelist: Mr. Atmanand,Staff ASIC Design Engineer,Infinera India Pvt. Ltd, Bangalore

Atmanand

He has over 16 years of experience specialized in ASIC Verification on various domains majorly focusing on communications, storage products.He has extensively worked from module level to Subsystem level to Full chip level verification of multiple multimillion gate designs. Lately he has also been working on post silicon validation of the ASICs.Prior to Infinera, I have worked with PMC-Sierra for 11+ years.. He holds a bachelor's degree in Electronics & Communication Engineering from the University of Dharwad. When I'm not working. I'm usually seen running.. Having done multiple HMs, aim to complete a FM sometime soon.


DFT Panelist: Manmeet,Sr. Engineering Manager,Intel Tech. India.

He leads the DFT and Test STA teams for Scalable Performance CPU Development Group ( SDG ) at Intel's Bangalore Development Centre for Server SOC's and baseband ASIC's focussing on DFT architecture definition, execution , early silicon bring-up's and quality silicon delivery in the hands of customer. He has varied background in various technology segments ranging from home entertainment devices, networking, graphics and mobile applications. Manmeet pays key focus on high reliability process, integration of latest methods to reduce test cost, achieve better quality by reducing DPPM's and achieving predictable success.


Verification Panelist: Siva Kumar Gowrisetti, Sr Manager, Western Digital

He manages pre-silicon verification of the "Client SSD controllers" at Western Digital. He has B.Tech (ECE) and M.S (VLSI) from JNTU Hyderabad and over 18 years of experience in ASIC/FPGA verification & design. Siva has earlier worked with AMD, Ineda, Qualcomm and has rich expertise in verification of processors, multimedia, Graphics, Game Consoles and ethernet-switch SoC's.


Verification Panelist: Sameer Kasture, Technical Lead, Open-Silicon Research Pvt. Ltd, a SiFive company

Coming Soon..

He is a part of semiconductor world for past 18 years and has witnessed multiple silicon success stories being a part of team.May it be behavioral models, custom SoCs, dedicated IPs, Sameer has a fair experience for all stages of the chip roadmap. All these years, Sameer has tried his hands at all stages of verification, gate-level simulations, occasional RTL design, ASIC architectures and even successful chip bring-ups.

Sameer gathered his diversified experience while being with companies like Conexant, Quartics, QLogic, Open-Silicon(present) to name some.Besides being in silicon world, Sameer enjoys a walk with nature on trekking, swimming, playing badminton, cricket and carrom.


Physical Design Panelist: Sarvesh Verma, Sr. Design Manager RnD, Intel

Coming Soon..

Technical leader and high-performance executive with 18+years of experience in VLSI design and implementation, acquired strong technology management and leadership expertise in domain by successfully participated in multiple tape outs of breakthrough SOCs and ASICs.Experienced in leading and managing projects in cellular and networking domains.

Was part of Motorola/FSL for 12+years and now with Intel for the last 6 years, working in Networking Customs Solutions team as part of Server Group where he drives the physical design implementation team for next generation base station ASICs/SOCs.He is deft at handling SoC implementation for complex million gate full chip designs and hold one US patent, one defensive publication and multiple internal/external conference publications


Design for Testability Panelist: Ajay Kumar Prajapati, Principal Engineer, Broadcom

Coming Soon..

Graduated in Bachelors of Technology in Electronics and communication from Nirma University Ahmedabad, Gujarat having industry experience of 14 Years. Authored paper "A novel approach to improve test coverage of BSR cells" publication date Nov 3, 2010 in IEEE-International Test Conference, Austin. Patent as SYSTEM FOR REDUCING TEST TIME USING EMBEDDED TEST COMPRESSION CYCLE BALANCING, date Filed May 8, 2014. Worked as Design/Sr Design Engineer in Freescale semiconductor for 7 years from 2004 to 2011 and currently working in Broadcom for 7 years as Principal Engineer. Worked on all aspects of Scan, Mbist, Bscan insertion and Verification and Silicon Bring-up for many successful SOCs with technology nodes ranging from 90nm to 16ffc.Currently working on defining DFT methodology for storage data controller devices. In free time enjoys reading books, playing cricket and travelling.


Design for Testability: Srinivasa Rao Billa, Sr Manager, Western Digital

Srinivas

Currently heading SIGNOFF team at Western Digital. Earlier worked with Texas Instruments, Ineda Systems and Open-Silicon. Have 17 years of experience in ASIC SoC design, Synthesis, STA(Signoff), DFT, early silicon bring-up, post-silicon char/qual and yield analysis. Also driven DFT methodology at Texas Instruments, Ineda Systems and Western Digital.


Physical Design Panelist: Tejinder Garg, Senior Principal Engineer, Broadcom Inc

Tejinder

Tejinder Garg holds M. Tech. (Microelectronics) with honors from Panjab University Chandigarh. Hhas 18 years of semiconductor industry experience. He has worked on complete design flow from RTL Design, Verification to Physical Design Implementation.

He has worked in different management positions in major semiconductor companies like Motorola, Freescale, Qualcomm, Intel and Broadcom. He has worked in multiple domains like Automotive, Mobile, IoT, STB and Cable Modem.


Hon'ble Jury Member ,

Coming Soon...